1. Field of the Invention
The present invention relates to a clock signal regulator circuit, which adjusts the phase of a clock signal provided to an integrated circuit such as an LSI integrated circuit.
2. Description of the Prior Art
Many electronic circuits of the present day contain LSI integrated circuits. To use such integrated circuits, a clock signal is required in order to synchronize and to operate each element of the circuit. In an actual circuit, in order to secure driving power[adg1], the clock signal is provided to each unit of the integrated circuit through several stages[adg2] of the driver. Many drivers are, therefore, used in the integrated circuit however, phase difference (clock skew) of the clock signal is caused by production tolerances in drivers, wiring and by other side effects. More specifically, the causes of the phase difference of the clock signal are variations in the transistors constituting the drivers, variation in width and thickness of the wiring pattern, variation in temperature of the integrated circuit and variation in voltage.
In the conventional method of LSI production, in order to prevent errors caused by phase differences, the phase difference is estimated and a structure is prepared to calculate the phase difference, by multiplying a preset variation coefficient by the phase of the reference clock.
The following Patent Documents 1 through 6 describe inventions relating to the phase adjustment of the clock signal. For example, Patent Document 1 (Japanese unexamined patent publication bulletin No. 2000-183730) describes a clock distribution system, which distributes the clock signal. The system comprises a phase comparison circuit, which compares the phases of the delayed clock signal with an external reference clock signal, counts based on the comparison result in the phase comparison circuit, and sets the delay time based on the count value.
Patent Document 2 (Japanese unexamined patent publication bulletin No. 11-273342) discloses an invention relating to a semiconducting memory device comprising a clock phase regulator circuit. The time period required until lock-on [adg3], is reduced by regulating the delay time immediately after power-on operation or immediately after coming out of standby mode.
Patent Document 3 (Japanese unexamined patent publication bulletin No. 10-336008) describes an invention, comprising a first DLL circuit, which outputs a roughly-adjusted clock by regulating the delay time of the received clock in stages, and a second DLL circuit for each of a plurality of entities, which outputs a plurality of clocks by regulating the delay time of the roughly-adjusted clock in stages. By comprising these two circuits, the phase of the clock signal is adjusted by the invention.
Patent Document 4 (Japanese unexamined patent publication bulletin No. 2002-94374) is with regard to an invention, comprising three S-R flip-flops, each consisting two AND gates, a NAND gate and an inverter. The maximum operating frequency is higher than the existing device so that the up-signal and the down-signal can be output according to the phase difference of both signals even if the phase difference between the reference clock signal and the clock signal is large.
Patent Document 5 (Japanese unexamined patent publication bulletin No. 08-190443) describes an invention, which enables sufficient reduction of skew when a group of logic circuits distributing the clock signal are not arranged uniformly in the clock distribution circuit.
In addition, Patent Document 6 (Japanese unexamined patent publication bulletin No. 2002-15569) describes an invention providing a semiconductor device which equalizes the delay time of the clock signal provided to a plurality of synchronous circuits. The device of the invention improves the synchronization by performing adjustments for each internal circuit even though the difference in the clock signal delay time is caused by the clock wiring.
However, in recent years, the situation is that because the clock frequency used in integrated circuits, such as LSI integrated circuits, has become very high and the corresponding time interval of a cycle extremely short, the slightest phase difference cannot be ignored. In addition, as integrated circuits continue to be miniaturized and as the degree of integration improves, the number of drivers and latches built into an LSI integrated circuit increases, and therefore, better control of the phase difference is now an imperative.
An approach is proposed where the phase difference (clock skew) is measured externally to the integrated circuit during production, and based on the measurement result, adjustment data is written to the driver. However, there is no proposal to realize automatic phase adjustment in the LSI integrated circuit.